VHD2VL v2.0 README.txt

Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
It does not support the full VHDL grammar - most of the testbench
related features have been left out.  See the examples and
translated_examples directories for examples of what vhd2vl can do.

Vhd2vl does a pretty good job of translating, but you should ALWAYS
use a formal verification tool to compare the generated Verilog with
the original VHDL!


1.0 HOW TO BUILD vhd2vl:

Just type 'make' in the src directory.

This version of vhd2vl has been tested with bison (GNU Bison) 1.875,
and flex version 2.5.4.


2.0 HOW TO USE vhd2vl:

   vhd2vl VHDL_file.vhd > VHDL_file.v

3.0 TROUBLESHOOTING:

If vhd2vl complains about a syntax error, this is usually due to a
VHDL construct that vhd2vl cannot translate.  Try commenting out the
offending line, and running vhd2vl again.  You can then edit the
Verilog output file and manually translate the offending line of VHDL.

Comments in the middle of statements sometimes confuse vhd2vl.  This
is a "feature" of the logic that copies comments from VHDL to Verilog.
If vhd2vl complains about a syntax error caused by a comment, just
move that comment out of the middle of the statement and try again.

The grammar has rules that recognize common ways of writing clocked
processes. Your code might contain clocked processes that do not match
any of the templates in the grammar.  This usually causes VHD2VL to
complain about a clock'event expression in a processa.  If this
happens, a minor rewrite of that process will let you work around the
problem.

If you need to look at the VHDL grammar, make puts a copy of it in
vhd2vl.output. If you need to change the grammar, then running vhd2vl
with the '-d' option will cause vhd2vl to trace how it is parsing the
input file.  (See the bison documentation for more details.)


4.0 IMPROVED VHDL LANGUAGE SUPPORT in v2.0:

The following VHDL constructs have been added in VHD2VL v2.0:

FOR LOOP

FOR GENERATE and IF GENERATE

natural, integer, time types

based numbers (16#55aa#)

expressions can now include VHDL type conversion functions, mod operator, numbers

now can tolerate comments in the middle of expressions

expressions can now be used in subscripts and vector range definitions

width on (others => 'x') can now be an expression

uses always @(*) when creating some combinational always blocks

variable initialization support

constant can be initialized by an expression

GENERIC definitions for entity are now translated into Verilog
parameter definitions, and GENERIC MAPs on instances are translated
into Verilog in-line explicit parameter definitions.

allow entity declarations and architectures in separate files

-d option for trace parse - to debug grammar errors

